1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory that can be completely or partially electrically erased at one fine and which is referred to as a flash memory. More particularly, this invention is concerned with a word line redundancy flash memory in which a faulty memory cells are replaced with redundant memory cell in units of a word line.
2. Description of the Related Art
In recent years, in the field of nonvolatile memories, efforts have been made to develop an element having a cell structure that enables electrical rewriting of data, permits low cost per bit, realizes downsizing, and offers a large storage capacity. This aims at replacement of magnetic memory media with semiconductor memories. A cell structure for realizing a large storage capacity and low cost is a one-transistor-per-one-cell structure in which, similarly to the cell structure of an EPROM, each cell has a single floating gate.
Even in a flash memory, redundancy, that is a technology for replacing faulty memory cells with spare redundant memory cells, is implemented in an effort to improve production yield.
When redundancy is implemented in a DRAM or SRAM, all memory cells on a row or column to which a faulty memory cell belongs are replaced. Specifically, assuming that the direction of a word line is regarded as a row and the direction of a bit line is regarded as a column, when row (word line) redundancy is attempted, one or more redundant word lines and memory cells to be connected on the rows of the word lines are prepared, and then a word line on which a faulty memory cell is connected is replaced with the redundant word line. Replacement can be repeated for the number of redundant word lines prepared. When column redundancy is attempted, similarly to the row redundancy, one or more redundant bit lines and memory cells to be connected on the columns of the bit lines are prepared, and then a bit line on which a faulty memory cell is connected is replaced with a redundant bit line.
In a conventional flash memory, row redundancy is difficult to realize because of an excessively erased cell. When excessive electrons are drawn out of a floating gate of a memory cell during erasure, the floating gate becomes positive. Even if the memory cell is unselected, leakage current flows through the bit line on which the memory cell is connected. As a result, reading cannot be achieved correctly. This memory cell is referred to as an excessive-erasure cell.
In a flash memory, as described above, erasing is achieved by applying high voltage to the common source line and grounding all word lines in a block. Since the word lines are grounded, the conditions for erasing are applied to all memory cells connected on the replaced word line. Writing is not performed to the memory cells connected to the replaced word line. Therefore, after erasing is executed several times, the memory cells are placed in an excessive-erasure state without fail. Therefore, row redundancy is difficult to implement in a flash memory.
Generally, word lines underlie bit lines. In the process of manufacturing, word lines are formed in an earlier stage than bit lines. The probability of occurrence of a fault resulting from adherent dust or the like is higher in word lines than in bit lines. It is therefore desired that not only bit-line redundancy but also word-line redundancy be performed.